Description Carte STM32-H743 NUCLEO-144 The STM32H743/753 lines contain the Arm® Cortex®-M7 core (with double-precision floating point unit) running up to 480 MHz. Performance de Carte STM32-H743 NUCLEO-144 480 MHz fCPU/, 2424 CoreMark /1027 DMIPS executing from Flash memory, with 0-wait states thanks to its L1 cache L1 cache (16 Kbytes of I-cache 16 Kbytes of D-cache) boosting execution performance from external memories Security de Carte STM32-H743 NUCLEO-144 STM32H753 MCUs include the following additional security features: Crypto/hash hardware acceleration Secure Firmware Install (SFI) embedded security services to authenticate and protect your software Ips while performing initial programming Secure Boot Secure Firmware Update (SBSFU) Power efficiency Multi-power domain architecture enables different power domains to be set in low-power mode to optimize the power efficiency. USB regulator to supply the embedded physical layer (PHY). 275 µ/MHz typical @VDD = 3.3 V and 25 °C in Run mode (peripherals off) 2.43 µA typical in Standby mode (low-power mode) 460 nA typical in VBAT mode with RTC (low-power mode) Graphics LCD-TFT controller interface with dual-layer support Chrom‑ART Accelerator™ enhances graphical content creation while saving core processing power, thus freeing up the MCU for other application needs JPEG hardware accelerator for fast JPEG encoding and decoding, off-loading the CPU Embedded peripherals Up to 35 communication interfaces including FD-CAN, USB 2.0 high-speed/full-speed, Ethernet MAC, camera interface Easily extendable memory range using the flexible memory controller with a 32-bit parallel interface, or the Dual-mode Quad-SPI serial Flash memory interface Analog: 12-bit DACs, fast 16-bit ADCs Multiple 16- and 32-bit timers running at up to 480 MHz on the 16-bit high-resolution timer The STM32H743/753 MCU line provides 1 to 2 Mbytes Flash memory, 1 Mbyte of SRAM with the following architecture: 192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data), 512 Kbytes, 288 Kbytes and 64 Kbytes of user SRAM, and 4 Kbytes of SRAM in backup domain to keep data in the lowest power modes and 100- to 240-pin packages in BGA and LQFP profiles.
